HY5DU281622 4 banks x 2m x 16bit double data rate sdram this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.2 / mar.00 description the hyundai HY5DU281622 is a 134,217,728-bit cmos double data rate(ddr) synchronous dram, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is orga- nized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the rising edges of the clock(falling edges of the clk ), data(dq), data strobes(ldqs/udqs) and write data masks(ldm/udm) inputs are sampled on both rising and falling edges of it. the data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. mode register set options include the length of pipeline ( cas latency of 2 / 2.5 ), the number of consecutive read or write cycles initiated by a single control command (burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), dq fet control (/qfc) and output driver types (full / half strength driver). because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2x higher data bandwidth can be achieved than that of traditional (single data rate) synchronous dram. features ? 2.5v v dd and v ddq power suppliy ? all inputs and outputs are compatible with sstl_2 interface ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? fully differential clock operations(clk & clk ) with 100mhz/125mhz/133mhz ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? data(dq) and write masks(ldm/udm) latched on both rising and falling edges of the data stobe ? data outputs on ldqs/udqs edges when read (edged dq) data inputs on ldqs/udqs centers when write (centered dq) ? delay locked loop(dll) installed with dll reset mode ? write mask byte controlled by ldm and udm ? bytewide data strobes by ldqs and udqs ? programmable cas latency 2 and 2.5 supported ? write operations with 1 clock write latency ? /qfc & half strength driver controlled by emrs ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal four bank operations with single pulsed ras ? auto refresh and self refresh supported ? 4096 refresh cycles / 64ms ordering information part no. power suppy clock frequency organization interface package HY5DU281622(l)t-k v dd =2.5v v ddq =2.5v 143mhz (*pc266a) 4banks x 2mbit x 16 sstl_2 400mil 66pin tsop ii HY5DU281622(l)t-h 133mhz (*pc266b) HY5DU281622(l)t-l 125mhz (*pc200) preliminary * jedec defined specifications compliant * (l) low power part
HY5DU281622 rev. 1.2 / mar.00 2 pin configuration 400 mil x 875mil 66 pin tsop-ii 0.65mm pin pitch top view vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd /qfc, nc ldm / we / cas / ras / cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm / clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 pin description pin pin name description clk, clk differential clock input the system clock input. all of the inputs are latched on the rising edges of the clock except dqi, ldqs/udqs and ldm/udm that are sampled on the both. cke clock enable controls internal clock signal and when deactivated, the ddr sdram will be one of the states among power down, suspend or self refresh. cs chip select enables or disables all inputs except clk/ clk , cke, l/udqs and l/udm. ba0, ba1 bank select address selects bank to be activated during either ras or cas activity. selects bank to be read/written during either ras or cas activity. a0 ~ a11 address row address : a0 ~ a11, column address : a0 ~ a8, ap flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operations. refer function truth table for details. ldm, udm write mask masks input data in write mode. ldqs, udqs data input/output strobe active on the both edges for data input and output. dq0 ~ dq15 data input/output multiplexed data input / output pin. v dd /v ss power supply/ground power supply for internal circuits and input buffers. v ddq /v ssq data output power/ground power supply for output buffers for noise immunity. v ref reference voltage reference voltage for inputs for sstl interface. /qfc (optional) dq fet switch control controls fet switches on dqs used for reduction of impedance. nc no connection no connection.
HY5DU281622 rev. 1.2 / mar.00 3 functional block diagram 4banks x 2mbit x 16 i/o double data rate synchronous dram absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 o c sec command decoder clk / clk cke / cs / ras / cas / we dm address buffer add bank control 2 mx16/bank0 column decoder column address counter sense amp 2- bit prefetch unit 2 mx16/bank1 2 mx16/bank2 2 mx16/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk ds write data register 2-bit prefetch unit ds dq[0:15] 32 16 16 32 clk_dll
HY5DU281622 rev. 1.2 / mar.00 4 dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. the value of v ref is approximately equal to 0.5v ddq . ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the s ame. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 1.15 1.25 1.35 v 3 parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 w series resistor (r s ) 25 w output load capacitance for access time measurement (c l ) 30 pf
HY5DU281622 rev. 1.2 / mar.00 5 capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.3v to 2.7v, v o dc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by design and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input capacitance a0 ~ a11, ba0 ~ ba1, cke, cs , ras , cas , we c in 2.0 3.0 pf clock capacitance clk, clk c clk 2.0 3.0 pf data input / output capacitance dq0 ~ dq15, ldqs, udqs, ldm, udm c io 4.0 5.0 pf v ref v tt v tt r t =50 w r t =50 w r s =25 w zo =50 w c l =30pf output
HY5DU281622 rev. 1.2 / mar.00 6 dc characteristics i (ta=0 to 70 c , voltage referenced to v ss = 0v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 2.7v dc characteristics ii (ta=0 to 70 c , voltage referenced to v ss = 0v) note : 1. i dd1 , i dd4 and i dd5 depend on output loading and cycle rates. specified values are measured with the output open. 2. min. of t rfc (auto refresh row cycle time) is shown at ac characteristics. 3. HY5DU281622t 4. HY5DU281622lt, self refresh low power parameter symbol min. max unit note input leakage current i li -5 5 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol - v tt - 0.76 v i ol = +15.2ma parameter symbol test condition speed unit note -k -h -l operating current i dd1 burst length=2, one bank active t rc 3 t rc (min), i ol =0ma 160 150 140 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 20 ma precharge standby current in non power down mode i dd2n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks 40 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 25 ma active standby current in non power down mode i dd3n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks 50 ma burst mode operating current i dd4 t ck 3 t ck (min), i ol =0ma all banks active cl=2.5 280 270 260 ma 1 cl=2 270 250 230 auto refresh current i dd5 t rc 3 t rfc (min), all banks active 330 ma 2 self refresh current i dd6 cke 0.2v 2 ma 3 tbd ma 4
HY5DU281622 rev. 1.2 / mar.00 7 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -k(pc266a) -h(pc266b) -l(pc200) unit note min max min max min max row cycle time t rc 65 - 65 - 70 - ns auto refresh row cycle time t rfc 75 - 75 - 80 - ns row active time t ras 45 120k 48 120k 50 120k ns row address to column address delay t rcd 20 - 20 - 20 - ns row active to row active delay t rrd 15 - 15 - 15 - ns column address to column address delay t ccd 1 - 1 - 1 - clk row precharge time t rp 20 - 20 - 20 - ns write recovery time t wr 15 - 15 - 15 - ns last data-in to read command t drl 1 - 1 - 1 - clk auto precharge write recovery + precharge time t dal 35 - 35 - 35 - ns system clock cycle time cas latency = 2.5 t ck 7 15 7.5 15 8 15 ns cas latency = 2 7.5 15 10 15 10 15 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 clk clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 clk data-out edge to clock edge skew t ac -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs t qh t hpmin -0.75ns - t hpmin -0.75ns - t hpmin -0.75ns - ns 1 clock half period t hp t ch/l min - t ch/l min - t ch/l min - ns 1 input setup time (fast slew rate) t is 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input setup time (slow slew rate) t is 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input hold time (slow slew rate) t ih 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input pulse width t ipw 2.2 2.2 - 6 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 clk write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 clk clk to first rising edge of dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 clk data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.5 - 0.6 - ns 7 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.5 - 0.6 - ns 7
HY5DU281622 rev. 1.2 / mar.00 8 ac characteristics (ac operating conditions unless otherwise noted) - continued - note : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, cs , ras , cas , we . 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns 5. ck, /ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation? 7. data latched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. write mask truth table note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. 2. in case of x16 data i/o, ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively. parameter symbol -k(pc266a) -h(pc266b) -l(pc200) unit note min max min max min max dq & dm input pulse width t dipw 1.75 - 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 clk read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 clk write dqs preamble setup time t wpres 0 - 0- - 0 - clk write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - clk write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 clk mode register set delay t mrd 2 - 2 - 2 - clk power down exit time t pdex 10 - 10 - 10 - ns exit self refresh to non-read command t xsnr 75 - 75 - 80 - ns exit self refresh to read cimmand t xsrd 200 - 200 - 200 - clk 8 average periodic refresh interval t refi - 15.6 - 15.6 - 15.6 us function cken-1 cken cs , ras , cas , we ldm udm addr a10/ ap ba note data write h x x l l x 1,2 data-in mask h x x h h x 1,2 lower byte write / upper byte-in mask h x x l h x 1,2 upper byte write / lower byte-in mask h x x h l x 1,2
HY5DU281622 rev. 1.2 / mar.00 9 simplified command truth table note : 1. ldm/udm states are ?don?t care?. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 11 and ba 0 ~ba 1 used for mode registering duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in clk(n), then there will be no command presented to activated bank until clk(n+bl/2+t rp ). 4. if a write with autoprecharge command is detected by memory component in clk(n), then there will be no command presented to activated bank until clk(n+bl/2+1+t dpl +t rp ). last data-in to prechage delay(t dpl ) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a 10 /ap is ?high? when row precharge command being issued, ba 0 /ba 1 are ignored and all banks are selected to be precharged. command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect h x h x x x x 1 no operation l h h h bank active h x l l h h ra v 1 read h x l h l h ca l v 1 read with autoprecharge h 1,3 write h x l h l l ca l v 1 write with autoprecharge h 1,4 precharge all banks h x l l h l x h x 1,5 precharge selected bank l v 1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entry h l l l l h x 1 exit l h h x x x 1 l h h h precharge power down mode entry h l h x x x x 1 l h h h 1 exit l h h x x x 1 l h h h 1 active power down mode entry h l h x x x x 1 l v v v 1 exit l h x 1 ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation )
HY5DU281622 rev. 1.2 / mar.00 10 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) package information 400mil 66pin thin small outline package
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